1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor device, and, more particularly, to a method for forming an interlayer dielectric film of a semiconductor device.
2. Description of the Related Art
Recently, as semiconductor diodes have become highly integrated, resulting in a gradual decrease in the design rule thereof, the gap between conductive patterns has also been narrowed. As a result, an importance of a gap-filling method for completely filling the gap between conductive patterns with an interlayer dielectric film covering the conductive patterns is emphasized. Generally, the interlayer dielectric film is formed by a chemical vapor deposition (CVD) process. When forming the interlayer dielectric film by use of a typical CVD process, an additional process of heat treating a wafer at a high temperature is performed after depositing the interlayer dielectric film in order to completely fill the fine gap formed between the conductive patterns without creating a void. However, when heating the wafer at a temperature of 850° C., the characteristics of the semiconductor diode are deteriorated.
Accordingly, processes of depositing an interlayer dielectric film, which can maximize its ability of filling the gap between metallic wires and is simple, have been suggested. On of such processes is a method for forming the interlayer dielectric film with a High Density Plasma (HDP) oxide film. With the method for forming the interlayer dielectric film with the HDP oxide film, after high density plasma is generated, a source gas supplied from the outside is ionized by the plasma, and is then chemically reacted with a wafer, whereby the interlayer dielectric film is deposited thereon. At this time, the process of depositing the HDP oxide film, and a process of etching the HDP oxide film are repeatedly performed so as to completely fill the narrow gap between the conductive patterns with the HDP oxide film.
However, the method as described above has problems in that the wafer is damaged by the plasma during the process of forming the HPD oxide film, and in that the wafer is further damaged by the other plasma processes subsequently performed thereafter or that the refresh property is lowered in the case of a semiconductor memory device, such as a dynamic random access memory (DRAM), due to current leakage caused by a hump property.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method for forming an interlayer dielectric film of a semiconductor device.
First, as shown in FIG. 1, a first interlayer dielectric film 110 is located on a semiconductor substrate 100 having an active region restricted by a trench isolation layer 102. A plurality of bit-line stacks 120 is located and spaced from each other on the first interlayer dielectric film 110. In some cases, other conductive patterns may be provided thereon. Each of the bit-line stacks 120 comprises a barrier pattern 121, a metallic film pattern 122 and a hard-mask film pattern 123, which are sequentially stacked. The barrier pattern 121 may be formed of a titanium/titanium nitride (Ti/TiN) film, and the metallic film pattern 122 may be formed of a tungsten (W) film. The hard-mask film pattern 123 may be formed of a nitride film. Each bit-line stack 120 is provided at either side with a bit-line spacer film 130.
Then, as shown in FIG. 2, an HDP oxide film 140 is formed as a second interlayer dielectric film on the first interlayer dielectric film 110 and the bit-line stacks 120 by use of a high density plasma apparatus. For this purpose, after loading the semiconductor structure of FIG. 1 into a chamber of the high density plasma apparatus, SiH4 as a source gas, and He as an added gas are supplied into the chamber together with the application of appropriate source power, thereby forming plasma 150 within the chamber. Then, an appropriate bias power is applied into the chamber such that ions excited into the plasma 150 are deposited onto a wafer, thereby allowing the HDP oxide film 140 to be deposited on the dielectric film 110 and the bit-line stacks 120. As this process is performed until the HDP oxide film 140 completely covers the bit-line stacks 120, the HDP oxide film 140 is formed as the second interlayer dielectric film. Although not shown in the drawings, an etching process is performed on the HDP oxide film 140 during the process described above.
However, with the conventional method for forming the interlayer dielectric film, a dangling bond may be formed in a boundary plane between the trench isolation layer 102 and the semiconductor substrate 100 due to the plasma. Since the dangling bond can have a negative influence on the characteristics of the semiconductor device, such as an increase in the current leakage, a subsequent H2/N2 annealing process must be performed in order to prevent such a phenomenon. Moreover, during the process of forming the HDP oxide film 140, carriers, for example electrons, can be accumulated in a gate oxide film through the metallic wires due to the plasma, and in this case, the current leakage is created at a lower gate, thereby deteriorating the refresh characteristic of the device.